Average Design Verification Engineer with Verilog VHDL Skills Salary in Vancouver, British Columbia
Annual Base Salary - $92,220.00/year
The average annual salary of Design Verification Engineer is $92,220.00
$0.00
Low
$92,220.00
Average
$93,960.00
High
The maximum salary range is between $93,960.00 and $108,054.00.
| Minimum Annual Pay | Maximum Annual Pay |
|---|---|
| $0.00 | $108,054.00 |
Bonus Range: 
$0.00 - $6,240.00
$0.00
$108,054.00
- Currency : CAD
- Annual Salary : $92,220.00
- Weekly Pay : $1,673.00
- Fortnightly Salary : $3,346.00
- Monthly Salary : $7,250.00
Design Verification Engineer Salary Comparison by Gender
This pie chart demonstrates the gender share for Design Verification Engineer. As indicated, the golden colour represents the percentage share for women and the green represents the percentage share for men.
As shown via chart, male employees are involved 100% in contrast with female who possibly are not a part of this profession.
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