Average Senior ASIC Engineer with Verilog VHDL Skills Salary in India
Annual Base Salary - ₹29,15,000.00/year
The average annual salary of Senior ASIC Engineer is ₹29,15,000.00
₹21,60,000.00
Low
₹29,15,000.00
Average
₹43,60,000.00
High
The starting salary of Senior ASIC Engineer is between ₹18,36,000.00 and ₹21,60,000.00 whereas the maximum salary range is between ₹43,60,000.00 and ₹50,14,000.00.
| Minimum Annual Pay | Maximum Annual Pay |
|---|---|
| ₹18,36,000.00 | ₹50,14,000.00 |
Profit Sharing: 
₹0.00 - ₹4,36,000.00
₹0.00
₹50,14,000.00
- Currency : INR
- Annual Salary : ₹29,15,000.00
- Weekly Pay : ₹52,885.00
- Fortnightly Salary : ₹1,05,769.00
- Monthly Salary : ₹2,29,167.00
Senior ASIC Engineer Salary Comparison by Gender
This pie chart demonstrates the gender share for Senior ASIC Engineer. As indicated, the golden colour represents the percentage share for women and the green represents the percentage share for men.
As shown via chart, male employees are involved 100% in contrast with female who possibly are not a part of this profession.
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