Average Design Verification Engineer with Verilog VHDL Skills Salary in New Delhi, Delhi
The average annual salary of Design Verification Engineer is ₹9,97,500.00
The maximum salary range is between ₹10,07,000.00 and ₹11,58,050.00.
| Minimum Annual Pay | Maximum Annual Pay |
|---|---|
| ₹0.00 | ₹11,58,050.00 |
- Currency : INR
- Annual Salary : ₹9,97,500.00
- Weekly Pay : ₹18,269.00
- Fortnightly Salary : ₹36,538.00
- Monthly Salary : ₹79,167.00
Design Verification Engineer Salary Comparison by Gender
This pie chart demonstrates the gender share for Design Verification Engineer. As indicated, the golden colour represents the percentage share for women and the green represents the percentage share for men.
As shown via chart, male employees are involved 100% in contrast with female who possibly are not a part of this profession.
Prominent Skills Affecting Design Verification Engineer Salary
The bar graph data indicates the importance of specific skills which can have a direct impact on Design Verification Engineer's salary. It clearly highlights the skills needed for a post of Design Verification Engineer when hired by an employer. The skill that is required for Design Verification Engineer is Verilog that affects the salary by 60%.
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